1. Field of the Invention
The present invention relates to circuitry for effecting multiplication of two field elements in a Galois field.
2. Description of the Prior Art
Error correcting codes are used for correcting code errors which may arise from defects, damages, or dust on a recording medium when digital data is recorded on or reproduced from the recording medium. Particularly in the field of digital audio recording and playback, BCH coding and Reed-Solomon coding have been relied upon in recent years. A device for correcting such code errors requires a multiplier for multiplying field elements in a Galois field, expecially a high-speed, low-cost multiplier.
Various such multipliers have been proposed thus far. One example of such a multiplier which is thought highest in speed and lowest in cost is disclosed in U.S. Pat. No. 4,037,093. The disclosed multiplier has (m-1) modulo multipliers connected in cascade at a first stage to which one input F is connected. At a second stage, bits of the output of these multipliers and bits of input F are gated respectively by bits of the other input P, thereby producing (m.times.m) partial products, which are summed to produce a final product at a third stage.
The total number of such partial products is m.sup.2, as described above. Therefore, as m gets larger, the number of the partial products increases vastly, with the result that the multiplier required is very large in size and high in cost, failing to operate at high speed.